Let \(W\) and \(M\) be binary machines and \(a\) a padding constant. One step of the logical simulator on a macrostep configuration with data equals the decorated form of one schedule-controller step, where the new finite data register, the single cell written under the guide head on each data tape, and the appended emission are exactly those returned by the data transducer evaluated at the current phase, register, input read, schedule tape reads, and the data cells under the guide head.

Suppose the base’s guide tape is the fixed guide of radius \(R\) and the simulator is in the forward phase with guide head at \(g \neq R + 1\). One step keeps the saved state, answer bit, and reads, moves the guide head to \(g+1\), replaces each neighbor register by the current payload decoded at \(g\), and rewrites cell \(g\) of each data tape to a data cell carrying its unchanged current payload with the old neighbor register cached; no output is emitted.

Suppose the base’s guide tape is the fixed guide of radius \(R\). From the forward phase with guide head at \(R + 1\), one simulator step enters the backward phase at position \(R\), resets every neighbor register to the blank payload, and leaves the saved state, answer bit, reads, data tapes, and output unchanged.

Suppose the base’s guide tape is the fixed guide of radius \(R\) and the simulator is in the backward phase with guide head at \(g \neq -R - 1\). One step moves the guide head to \(g - 1\), replaces each neighbor register by the current payload decoded at \(g\), and rewrites cell \(g\) of each data lane to a data cell with blank cached neighbor whose current payload is chosen by that lane’s virtual head direction: the cached left neighbor for a leftward move, the unchanged current payload for a stationary move, and the carried register for a rightward move.

Suppose the base’s guide tape is the fixed guide of radius \(R\). From the backward phase with guide head at \(-R - 1\), one simulator step enters the return phase at position \(-R\) and leaves the finite data register, data tapes, and output unchanged.

Suppose the base’s guide tape is the fixed guide of radius \(R\), let \(f\) assign a payload vector to every integer coordinate, and suppose every current payload of the data tapes decodes to \(f\). For every \(n \le 2R + 1\), running the simulator \(n\) steps from the forward phase at \(-R\) with neighbor registers \(f(-R-1)\) stays in the forward phase, reaching position \(-R+n\) with neighbor registers \(f(-R+n-1)\), on tapes whose current payloads still decode to \(f\) and whose cached left-neighbor payloads equal \(f(z-1)\) at every visited coordinate \(-R \le z \lt -R + n\).

Suppose the base’s guide tape is the fixed guide of radius \(R\), let \(f\) assign a payload vector to every coordinate, and suppose the current payloads of the data tapes decode to \(f\) while the cached left neighbors equal \(f(z-1)\) throughout \([-R, R]\). For every \(n \le 2R + 1\), running the simulator \(n\) steps from the backward phase at \(R\) with neighbor registers \(f(R+1)\) stays in the backward phase, reaching position \(R - n\) with neighbor registers \(f(R-n+1)\), on tapes whose current payload on lane \(i\) at coordinate \(z\) is the shifted value \(f(z + m_i)\) for visited coordinates \(R - n \lt z \le R\) — where \(m_i\) is the virtual head direction of lane \(i\) selected from the saved state and reads — and the unshifted value \(f(z)\) elsewhere, while the cached left neighbors remain \(f(z-1)\) for \(-R \le z \le R - n\).

Suppose the base’s guide tape is the fixed guide of radius \(R\). Running the simulator exactly \(R + 2\) steps from the leftward-seek phase with guide head at the origin and blank neighbor registers reaches the forward phase at \(-R\) with blank neighbor registers, leaving the saved state, answer bit, reads, data tapes, and output unchanged.

Suppose the base’s guide tape is the fixed guide of radius \(R\). Running the simulator exactly \(R + 1\) steps from the return phase with guide head at \(-R\) and unary head at \(u\) reaches the counter-test phase with unary head \(u + 1\) and guide head at the origin; the simulated state is replaced by the successor state of the source action selected from the saved state and reads, while the answer bit, reads, neighbor registers, data tapes, and output are unchanged.

Suppose the base’s unary tape holds a unit marker at \(u\). One simulator step from the counter-test phase saves the current payloads decoded at the origin as the new reads, updates the answer register to the bit emitted by the source action selected from the saved state and those reads (keeping the old answer when nothing is emitted), performs that action’s optional work-lane writes at the origin, clears the neighbor registers to blank, and enters the leftward-seek phase; no output is emitted.

Let \(M\) be a binary machine and \(c\) a configuration of \(M\), and suppose the current payloads of the data tapes decode to the head-centered payload vectors of \(c\). After writing at the origin of each work lane the symbol optionally written by the totalized action of \(M\) at \(c\) (with blank cached neighbor, the input lane untouched), the current payloads decode to the written payload vectors of \(c\) under that action.

Suppose the base’s guide tape is the fixed guide of radius \(R\), the current payloads of the data tapes decode to \(f\), and the boundary values \(f(-R-1)\) and \(f(R+1)\) are blank. Then running the simulator exactly \(6R + 7\) steps from the leftward-seek phase at the origin with unary head \(u\) and blank neighbor registers reaches the counter-test phase with unary head \(u + 1\), simulated state equal to the successor state of the source action selected from the saved state and reads, and neighbor registers \(f(-R)\), on tapes whose current payload on lane \(i\) at coordinate \(z\) is \(f(z + m_i)\) for \(-R \le z \le R\) and \(f(z)\) outside, where \(m_i\) is that lane’s selected virtual head direction.

For a binary machine \(M\), a configuration \(c\) of \(M\), and any offset \(z \neq 0\), the written payload vector of \(c\) under the totalized action of \(M\) agrees at \(z\) with the head-centered payload vector of \(c\).

Suppose the base’s guide tape is the fixed guide of radius \(R\) and its unary tape holds a unit marker at \(u\), and let \(c\) be a configuration of the source \(M\) whose head-centered payload vectors are decoded by the data tapes and are blank outside \([-R, R]\), as are those of its one-step successor. Then exactly \(6R + 8\) simulator steps from the counter-test phase carrying the state and last-emitted bit of \(c\) reach the counter-test phase at unary head \(u + 1\) carrying the state and last-emitted bit of the successor of \(c\), with data tapes decoding the successor’s head-centered payload vectors and an unchanged output stream.

For every binary machine \(M\) and word \(x\), the copied payloads of count \(|x| + 1\) coincide with the head-centered payload vectors of the initial configuration of \(M\) on \(x\): the input lane carries the complete virtual input including both boundary tags, and every work lane is blank.

If every current payload of the data tapes is blank, then after the copy write placing the left-boundary payload (blank content with tag \(1\)) at coordinate \(-1\), the current payloads are exactly the copied payloads of count \(0\).

If the current payloads of the data tapes are the copied payloads of count \(j\), then after the copy write placing the virtual input payload of \(x\) at position \(j\) at coordinate \(j\), the current payloads are the copied payloads of count \(j + 1\).

For any configuration of a multi-tape machine on an input word \(x\), the input read is blank if and only if the input head is at position \(0\) or at position \(|x| + 1\).

Let \(x\) be a binary word embedded letterwise into the simulation alphabet, and let a configuration on this embedded input have its input head at position \(j + 1\) with \(j \le |x|\). Then the input read is the bit symbol of \(x_j\) when \(j \lt |x|\), and blank when \(j = |x|\); this includes the empty input.

Let \(x\) be a binary word embedded into the simulation alphabet and let a configuration on the embedded input have its input head at position \(j + 1\) with \(j \le |x|\). Then the payload whose content is the clock-bit decoding of the input read and whose tag is the right-boundary tag \(2\) when the read is blank and the ordinary tag \(0\) otherwise is exactly the virtual input payload of \(x\) at position \(j\).

Applying to a schedule configuration a non-clock action of the schedule controller — with a target phase, an input move, and optional writes and moves on the three distinguished tapes — the preparation invariant of the resulting configuration equals the preparation condition at the target phase, the moved input position, the unary and guide head positions shifted by the action’s moves, and the unary tape after the action’s optional write, with the data register, data tapes, and output unchanged.

If a tape carries the origin sentinel exactly at coordinate \(0\), then after writing a unit marker at any coordinate \(u \ge 1\) it still carries the origin sentinel exactly at coordinate \(0\).

Let a schedule configuration \(c\) on the embedded input be in a live phase and satisfy the preparation invariant with a given data register, data tapes, and output. Then the preparation invariant holds for the configuration after one step of the schedule controller, taken with the register, guide-position tape writes, and appended emission produced by the data transducer’s visit at \(c\).

For all binary machines \(W\) and \(M\), padding constant \(a\), word \(x\), and time \(t\), there exist a data register, data tapes, and an output list such that the \(t\)-step run of the logical simulator from its initial configuration on the embedded input equals the decorated form of the schedule controller’s \(t\)-step run with these components, and the preparation invariant holds for that schedule configuration with these components.

Rebuilding a schedule configuration in macrostep form from its own state and its actual unary and guide head positions returns the configuration itself.

Let \(W\) compute on every input \(x\) the binary expansion of \(T(|x|)\) within \(b\, (T(|x|)+1)\) steps, and suppose \(n \le T(n)\) for all \(n\). Then for every word \(x\) there is a time \(t\) at which the schedule controller built from \(W\) and \(a\), run on the embedded input, is in the counter-test phase with unary head at \(1\), guide head at the origin, unary counter tape with \((a+1)(T(|x|)+1)\) markers, and guide tape of radius \(3(a+1)(T(|x|)+1)\).

Let \(W\) compute on every input \(x\) the binary expansion of \(T(|x|)\) within \(b\, (T(|x|)+1)\) steps, and suppose \(n \le T(n)\) for all \(n\). Then for every word \(x\) there are a time \(t\), a base schedule configuration whose unary tape has \((a+1)(T(|x|)+1)\) markers and whose guide tape has radius \(3(a+1)(T(|x|)+1)\), and data tapes decoding the head-centered payload vectors of the initial configuration of the source \(M\) on \(x\), such that the \(t\)-step run of the logical simulator on the embedded input is the macrostep configuration with data at the counter-test phase, unary head \(1\), guide head at the origin, initial data register, and empty output.

Let the base configuration’s unary tape have \(B\) markers with \(|x| + 1 \le B\) and its guide tape have radius \(3B\), and let the data tapes decode the head-centered payload vectors of the initial configuration of the source \(M\) on \(x\). Then for every \(j \le B\) there are reads, neighbor registers, and data tapes such that \(j\, (18B + 8)\) simulator steps from the first counter-test configuration reach the counter-test phase with unary head \(j + 1\), carrying the state and last-emitted bit of the \(j\)-step run of \(M\) on \(x\), with data tapes decoding that run’s head-centered payload vectors and no output emitted.

If the base’s unary tape does not hold a unit marker at \(u\), then for every data register and all data tapes, one simulator step from the counter-test phase with empty output halts, and its output is the single bit symbol carrying the saved answer bit of the register.

Let \(W\) compute on every input \(x\) the binary expansion of \(T(|x|)\) within \(b\, (T(|x|)+1)\) steps, suppose \(n \le T(n)\) for all \(n\), and let \(M\) decide the language \(L\) within time \(a\, T(n)\). Then for every word \(x\) there is a time \(t\) within which the logical simulator, on the embedded input, computes the one-symbol output consisting of the bit symbol of the indicator of \(L\) at \(x\).

Let \(W\) compute on every input \(x\) the binary expansion of \(T(|x|)\) within \(b\, (T(|x|)+1)\) steps, suppose \(n \le T(n)\) for all \(n\), and let \(M\) decide the language \(L\) within time \(a\, T(n)\). Then the candidate simulator built from \(W\), \(M\), and \(a\) decides \(L\) within time \(\bigl(18(a+1)^2 + 23(a+1) + 3b + 25\bigr)\, (T(n)+1)^2\).